1. Field
The present invention relates to a fabrication method of a liquid crystal display device (LCD), and particularly, to a method for forming a contact hole connecting source and drain electrodes and an active layer of a thin film transistor (TFT).
2. Description of the Related Art
A liquid crystal display panel includes TFT array layer, color filter layer corresponding to the TFT array layer and liquid crystal layer therebetween. The TFT array layer includes a plurality of unit pixels arranged in a matrix form and the color filter substrate includes color filter layer to display information as color.
The unit pixels on the TFT array substrate are defined by a plurality of gate lines and a plurality of data lines which perpendicularly intersect with the gate lines, and a TFT for driving the unit pixel is formed at an intersection of the gate line and the data line.
While an amorphous silicon TFT including an active layer made of amorphous silicon has been primarily used in LCDs, other types of TFTs are currently being investigated. One such type of TFT under development is a polycrystalline silicon (polysilicon) TFT including an active layer made of polysilicon and having an operation characteristic that is better than the TFT having an active layer made of amorphous silicon layer.
A structure of a polysilicon TFT will now be described with reference to FIG. 1. The polysilicon TFT includes a buffer layer 2, a silicon oxide (SiO2) layer formed on a transparent substrate 1 such as glass, plastic or the like, and an active layer 3 made of polysilicon and formed on the buffer layer 2. A first insulation layer 4 for insulating the polysilicon layer is formed on the polysilicon active layer 3.
A gate electrode 5 is formed on the first insulation layer 4, and a second insulation layer 6 is formed on the gate electrode 5. The second insulation layer 6 is a silicon oxide (SiO2) layer and insulates source and drain electrodes 7 and 8 to be formed on the second insulation layer 6 from the gate electrode 5. A source electrode 7 and a drain electrode 8 for applying a data signal to a pixel electrode 10 are formed on the second insulation layer 6. The source and drain electrodes 7 and 8 are connected to the active layer 3 through contact holes 20 through the first insulation layer 4 and the second insulation layer 6.
In addition, a passivation layer 9 is formed on the source and drain electrodes 7, 8 so as to protect the TFT formed under the passivation layer 9 and flatten the liquid crystal display device in which the TFT is fabricated. A contact hole 30 for connecting the drain electrode 8 and the pixel electrode 10 to each other is formed at the passivation layer 9, and the pixel electrode 10 is connected to the drain electrode 8 through the contact hole 30.
Hereinafter, a process for forming a contact hole 20 connecting the source and drain electrode 7 and 8 to the active layer 3 will now be described in detail with reference to FIG. 2.
A second insulation layer 6 is formed on a gate electrode 5, and then a photoresist layer 11 is formed on the second insulation layer 6. When the photoresist layer 11 is exposed and developed by using a mask, a contact hole pattern is formed as shown in FIG. 2. Wet-etching is performed using the photoresist layer 11 including the contact hole pattern as a mask, thereby etching the second insulation layer 6 and then the first insulation layer 4.
Because wet-etching is isotropic, the second insulation layer 6 may be excessively etched under the photoresist pattern, and this etched-away portion is called undercut. Undercutting leads to a contact hole that does not satisfy a desired design rule, and thus the source and drain electrodes are formed to be larger than the desired design rule. In addition, undercutting causes a stepped contact hole 20 to be formed as shown by the first insulation layer 4 and the second insulation layer 6 in FIG. 2. If a metal thin layer for source/drain electrodes is deposited in the stepped contact hole 20 described above, the formed thin layer may be disconnected.
Thus, forming a contact hole by wet-etching does not permit satisfaction of a desired design rule, and undercut occurs. In order to solve such problems, techniques using silicon nitride layer as a second insulation layer have been introduced. In this method, the first and second insulation layers are etched by dry-etching.
However, while a silicon nitride layer is able to be dry-etched easily, a silicon oxide layer is not. This means that, as the first insulation layer 4 is etched, the photoresist layer used as a mask is hardened and thus is not easily removed in a stripping process subsequent to the etching process. Thus, photoresist residue remains as a foreign substance. The photoresist residue causes various connection problems between the TFT and other circuitry in the LCD.
In addition, because the etching speed of the second insulation layer 6 is different from that of the first insulation layer 4, undercut of the first insulation layer 4 occurs when the first insulation layer is etched, and thus a stepped portion is again generated in the contact hole. When source and drain electrodes are formed using the contact holes having a stepped portion, connection problems between the source and drain electrodes and the TFT may occur.